The present invention relates to a graphics system.
Graphics systems are well known in the industry concerned with the display of images on cathode ray tube screens employing line by line scanning. The image elements, or pixels, are stored in a dynamic DRAM memory.
In such a graphics system, the DRAM memory is driven, in read and in write, by various processing modules which formulate requests for access. These requests may be simultaneous, while their execution cannot be so, and it is therefore necessary to provide arbitrating means. In order to do this, a known priority logic system is described in French Patent Application No. 2,593,304, which application corresponds to U.S. Pat. No. 819,727 filed on 17 January 1986 by the company Intel, the implementation of which is found in the INTEL graphics controller No. 82786 as described in the technical brochure AP270, especially on p.19. This known system provides various parametric registers, according to the choice of the user, to allocate priorities to the requests for access. This solution is relatively complex, and the user must proceed by successive trials in order to find the parameters giving the highest performance levels, and furthermore the technical construction of the described device is relatively expensive.